What are the architectural differences between Qualcomm Snapdragon X, Intel Core Ultra, and AMD Ryzen AI NPUs for Copilot+ PCs?

 

Qualcomm, Intel, and AMD all meet Microsoft’s minimum 40+ TOPS requirement for Copilot+ PCs, but they achieve this performance through fundamentally different microarchitectural philosophies. Their NPUs stem from different lineages: mobile DSPs, computer vision VPUs, and spatial FPGA fabrics.

1. Qualcomm Hexagon NPU (Snapdragon X Series)

• Architectural Lineage: Evolution of Qualcomm’s VLIW (Very Long Instruction Word) Digital Signal Processor (DSP).

• Topology: Fused SIMD/VLIW Pipeline. Rather than using distinct isolated cores, the Hexagon NPU fuses Scalar, Vector (HVX), and Tensor (HTP) processing engines around a central, shared local memory buffer.

• Execution Model: Instruction-driven parallel execution leveraging Simultaneous Multithreading (SMT) to mask memory latency. It processes data in tiny memory segments using micro-tile inferencing.

+-------------------------------------------------------------+
|                      QUALCOMM HEXAGON                       |
|  +-------------------------------------------------------+  |
|  |           Large Dedicated Shared SRAM                 |  |
|  +-------------------------------------------------------+  |
|          ^                       ^               ^          |
|          v                       v               v          |
|  [ Scalar Engine ]     [ Vector Engine ]  [ Tensor Engine ] |
+-------------------------------------------------------------+

• Key Strengths:

  • Unified Local Memory: Accelerators pass data directly to each other via internal SRAM without writing intermediate activation states back to main system DRAM.

  • Energy Efficiency: Exceptional performance-per-watt during continuous background inference (e.g., live eye-tracking or background blur).

• Peak Compute: 45 TOPS.

2. Intel NPU 4 (Core Ultra 200V / Lunar Lake)

• Architectural Lineage: Derived from Intel’s acquisition of Movidius VPU (Vision Processing Unit) technology.

• Topology: Tile-Based Neural Compute Engines (NCE). Intel NPU 4 scales performance by packing 6 dedicated NCE tiles onto the Compute Tile.

• Execution Model: Hardware-scheduled execution where each NCE operates as an autonomous processing unit.

+-------------------------------------------------------------+
|                       INTEL NPU 4                           |
|  +-------------------------------------------------------+  |
|  |          Dedicated Tile L2 / Scratchpad SRAM          |  |
|  +-------------------------------------------------------+  |
|      |               |               |               |      |
|  [ NCE 1 ]       [ NCE 2 ]       [ NCE 3 ]     ... [ NCE 6 ]|
|  • MAC Array     • MAC Array     • MAC Array     • MAC Array|
|  • Vector Reg    • Vector Reg    • Vector Reg    • Vector Reg|
|  • Prog. DSP     • Prog. DSP     • Prog. DSP     • Prog. DSP|
+-------------------------------------------------------------+

• Inside Each NCE: Contains a high-throughput Multiply-Accumulate (MAC) array, a vector register file, a dedicated DMA engine, and a programmable DSP.

• Key Strengths:

  • Programmable DSP Cores: Allows developers to execute non-standard or custom activation functions inside the NPU without falling back to CPU/GPU execution.

  • Large Scratchpad SRAM: Features a high-bandwidth local L2 scratchpad cache directly on the NPU tile, preventing DRAM bottlenecks when streaming weights for large transformer models.

• Peak Compute: 48 TOPS.

3. AMD XDNA 2 NPU (Ryzen AI 300 Series)

• Architectural Lineage: Derived from Xilinx’s Versal Adaptive SoC AI Engine (AIE) spatial architecture.

• Topology: Spatial Dataflow Tiled Array. Features a 2D mesh matrix containing 32 AI Engine (AIE-ML v2) tiles connected via a non-blocking interconnect.

• Execution Model: Deterministic spatial streaming. Instead of relying on a traditional cache hierarchy, data streams from tile to tile across the 2D grid. Tile $A$ outputs directly into Tile $B$'s local memory.

+-------------------------------------------------------------+
|                        AMD XDNA 2                           |
|    [ AIE Tile 1,1 ] <---> [ AIE Tile 1,2 ] <---> [ AIE 1,3 ]|
|          ^                      ^                   ^       |
|          v                      v                   v       |
|    [ AIE Tile 2,1 ] <---> [ AIE Tile 2,2 ] <---> [ AIE 2,3 ]|
|          ^                      ^                   ^       |
|          v                      v                   v       |
|    [ AIE Tile 3,1 ] <---> [ AIE Tile 3,2 ] <---> [ AIE 3,3 ]|
|   (Each Tile: VLIW/SIMD Vector + RISC Scalar + Local Mem)   |
+-------------------------------------------------------------+

• Key Strengths:

  • Block FP16 Data Type: Supports native Block Float 16, which groups 8 values under a shared exponent. It uses ~9 bits per value instead of 16 bits, delivering the mathematical precision of FP16 with the bandwidth and energy efficiency of INT8.

  • Zero Cache Miss Latency: Deterministic dataflow eliminates cache miss stalls, making inference times predictable.

• Peak Compute: 50–55 TOPS.

Architectural Comparison Matrix

Architectural Feature
Qualcomm Hexagon
Intel NPU 4
AMD XDNA 2

Primary Design Focus
Low-power mobile inferencing
Programmable host acceleration
Deterministic spatial dataflow

NPU Layout
Fused Scalar/Vector/Tensor pipeline
6 Autonomous NCE cores
32 Spatial AIE tiles in a 2D grid

Peak NPU Compute
45 TOPS
48 TOPS
50–55 TOPS

Memory Strategy
Shared internal SRAM & Micro-tiles
Dedicated L2 Scratchpad SRAM
Tile-to-tile streaming local SRAM

Precision Support
INT8, INT16, FP16
INT8, FP16, BF16
INT8, FP16, Block FP16

Execution Paradigm
Instruction-driven (VLIW / SMT)
Core/Engine execution with onboard DSP
Spatial pipeline (FPGA-derived)